(China (Mainland))
Product Summary
The ADSP21161NKCA-100 is a SHARC Processor. The ADSP21161NKCA-100 is a low cost derivative of the ADSP-21160 featuring Analog Devices Super Harvard Architecture. Easing portability, the ADSP-21161N is source code compatible with the ADSP-21160 and with first generation ADSP21161NKCA-100 in SISD (Single-Instruction, Single-Data) mode. Like other SHARC DSPs, the device is a 32-bit processor that is optimized for high performance DSP applications. The ADSP21161NKCA-100 includes a 100 MHz or 110 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.
Parametrics
ADSP21161NKCA-100 absolute maximum ratings: (1)Internal (Core) Supply Voltage (VDDINT): -0.3 V to +2.2 V; (2)Analog (PLL) Supply Voltage (AVDD): -0.3 V to +2.2 V; (3)External (I/O) Supply Voltage (VDDEXT): -0.3 V to +4.6 V; (4)Input Voltage: -0.5 V to VDDEXT + 0.5 V; (5)Output Voltage Swing: -0.5 V to VDDEXT + 0.5 V; (6)Load Capacitance: 200 pF; (7)Storage Temperature Range: -65℃ to +150℃.
Features
ADSP21161NKCA-100 features: (1)Two processing elements, each made up of an ALU, multiplier, shifter, and data register file; (2)Data address generators (DAG1, DAG2); (3)Program sequencer with instruction cache; (4)PM and DM buses capable of supporting four 32-bit data transfers between memory and the core every core processor cycle; (5)Interval timer; (6)On-Chip SRAM (1M bit); (7)SDRAM controller for glueless interface to SDRAMs; (8)External port that supports:; (9)Interfacing to off-chip memory peripherals; (10)Glueless multiprocessing support for six ADSP-21161N SHARCs; (11)Host port read/write of IOP registers; (12)DMA controller; (13)Four serial ports; (14)Two link ports; (15)SPI compatible interface; (16)JTAG test access port; (17)12 general-purpose I/O pins.
Diagrams
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